High voltage SOI semiconductor device

ABSTRACT

In an SOI (Silicon On Insulator) semiconductor device, a first semiconductor layer overlies a semiconductor substrate so as to sandwich an insulating layer, and second and third semiconductor layers with a different conductivity type from the second semiconductor layer are formed on the surface of the first semiconductor layer. At the interface between the first semiconductor layer and the insulating layer, a fourth semiconductor layer with a different conductivity type from the first semiconductor layer is formed. The fourth semiconductor layer includes an impurity of larger than 3×10 12 /cm 2  so as not to be completely depleted even though a reverse bias voltage is applied between the second and third semiconductor layers.

BACKGROUND OF THE INVENTION

(1)Field of the Invention

The present invention relates to an SOI (Silicon On Insulator)semiconductor device, and especially relates to a technology ofimproving the operating voltage of the SOI semiconductor device.

(2)Related Art

In order to electrically separate the semiconductor elements in asemiconductor integrated circuit, the dielectric isolation is oftenused. In the dielectric isolation, insulating layers are formed at thebottom and on the side of the semiconductor layer, which is the activelayer of the semiconductor device. In this specification, this structureis referred to “dielectric isolation structure”.

The SOI semiconductor device with the dielectric isolation structuresolves problems facing the conventional semiconductor device using thepn junction isolation, i.e., leakage current via the pn junction andunexpected bipolar effects. The SOI semiconductor device with thedielectric isolation structure is effectively used as the high voltagesemiconductor device and the semiconductor device for analog switch.

The conventional SOI semiconductor device is disclosed in JapanesePatent Nos. 2896141 and 2878689.

Each of FIGS. 1 and 2 shows the structure of an n-type high voltage MOS(Metal Oxide Semiconductor) transistor as an example of the conventionalSOI semiconductor device. An n-type high voltage MOS transistor 100 inFIG. 1 is manufactured as follows. A silicon dioxide film 102 is formedon a main surface of a semiconductor substrate 101, which is asupporting substrate of the SOI substrate. Then, an n⁻-typesemiconductor layer 103, which is to be the active layer of the SOIsubstrate, overlies the silicon dioxide film 102. An isolation trench104 extending to the silicon dioxide film 102 is formed on the n⁻-typesemiconductor layer 103 by etching so as not to be affected by thepotentials of the adjacent semiconductor elements. On the side walls ofthe isolation trench 104, silicon dioxide films 105 are formed. Theisolation trench 104 is filled with polysilicon 106. As a result, then⁻-type semiconductor layer 103 is electrically isolated from the othersemiconductor island. More specifically, the n⁻-type semiconductor layer103 is an island dielectrically isolated by the silicon dioxide films102 and 105.

On the surface of the island n⁻-type semiconductor layer 103, gate oxidefilms 107, gate electrodes 108, a p-type semiconductor layer 109, asource electrode 112, n⁺-type semiconductor layers 110 and 111, anddrain electrodes 113 are formed to form the n-type high voltage MOStransistor 100. The p-type semiconductor layer 109 is formed to form achannel region. The n⁺-type semiconductor layers 110 are connected tothe source electrode 112 and surrounded by the p-type semiconductorlayer 109. The n⁺-type semiconductor layers 111 are connected to thedrain electrodes 113.

An n-type high voltage MOS transistors 150 in FIG. 2 has almost the samestructure as the n-type high voltage MOS transistor 100 in FIG. 1. Then-type high voltage MOS transistor 150 is different from the n-type highvoltage MOS transistor 100 in forming an n⁻-type semiconductor layer 114between the n⁻-type semiconductor layer 103 and the silicon dioxide film102 and forming an n⁺-type semiconductor layer 115 between the n⁻-typesemiconductor layer 103 and the silicon dioxide film 105 so as toconnect to the bottom of the n⁺-type semiconductor layers 111. Here, theimpurity concentration is set as relatively low in the n⁻-typesemiconductor layer 114 and the n⁺-type semiconductor layer 115. Bydoing so, a depletion layer is also formed around the n⁻-typesemiconductor layer 114 and the n⁺-type semiconductor layer 115 in then⁻-type semiconductor layer 103 so as to improve the operating.

Generally speaking, a voltage of 0V is applied to a semiconductorsubstrate 101 in the n-type high voltage MOS transistors 100 and 150 inFIGS. 1 and 2. When the potential of the p-type semiconductor layer 109is almost the same as the potential of the semiconductor substrate 101,and a large and positive voltage is applied to the n⁺-type semiconductorlayers 111, a pn junction diode consisting of the p-type semiconductorlayer 109 and the n⁻-type semiconductor layer 103 is in a reverse biasstate. In this case, a depletion layer extends from the interfacebetween the p-type semiconductor layer 109 and the n⁻-type semiconductorlayer 103. Due to the large and positive voltage applied to the n⁺-typesemiconductor layers 111, the voltage of 0V applied to the semiconductorsubstrate 101, and the voltage applied to the p-type semiconductor layer109, the depletion layer evenly extends in the n⁻-type semiconductorlayer 103 to reduce the internal electric field.

As a result, avalanche breakdown hardly occurs in the n⁻-typesemiconductor layer 103. The operating voltage of the n-type highvoltage MOS transistor depends on the occurrence of the avalanchebreakdown in the n⁻-type semiconductor layer 103. Accordingly, avalanchebreakdown prevention can improve the operating voltage in the reversebias state.

In the conventional SOI semiconductor device, however, especially, whenthe potential of the n⁺-type semiconductor layers 111 that are connectedto the drain electrodes 113 is almost the same as the potential of thesemiconductor substrate 101 as the supporting substrate of the SOIsubstrate, a depletion layer is not sufficiently formed in the n⁻-typesemiconductor layer 103. As a result, the operating voltage in thereverse bias state, which mainly depends on the avalanche breakdown,conspicuously deteriorates.

More specifically, in the reverse bias state, in which a large andnegative voltage is applied to the p-type semiconductor layer 109, ageneral voltage of 0V is applied to the semiconductor substrate 101, anda voltage of 0V is applied to the n⁺-type semiconductor layers 111, thesemiconductor substrate 101 and the n⁺-type semiconductor layers 111 areat the same potential. This adversely affects the extension of thedepletion layer. As a result, the depletion layer extending from the pnjunction interface of the between the p-type semiconductor layer 109 andthe n⁻-type semiconductor layer 103 does not sufficiently extend toreach regions of the n⁻-type semiconductor layer 103 under the n⁺-typesemiconductor layers 111. Accordingly, the electric field strengtharises in the n⁻-type semiconductor layer 103 and the avalanchebreakdown tends to occur to drastically deteriorate the reverse biasvoltage of the n-type MOS transistor.

As has been described, the operating voltage cannot be kept relativelyhigh in any reverse bias state according to the conventional SOIsemiconductor device structure. The avalanche breakdown tends to easilyoccur to deteriorate the operating voltage in a specific condition.

SUMMARY OF THE INVENTION

It is accordingly the object of the present invention to provide an SOIsemiconductor device with relatively high operating voltage in anyreverse bias state.

The above-mentioned object may be achieved by an SOI semiconductordevice including: a first semiconductor layer; a second semiconductorlayer that is formed on a first part of a first main surface of thefirst semiconductor layer; a third semiconductor layer with aconductivity type different from a conductivity type of the secondsemiconductor layer, the third semiconductor layer being formed on asecond part of the first main surface of the first semiconductor layer,the second part being separated from the first part; a fourthsemiconductor layer with a conductivity type different from aconductivity type of the first semiconductor layer, he fourthsemiconductor layer being formed on a second main surface of the firstsemiconductor layer; and a first insulating layer that is formed on amain surface of the fourth semiconductor layer opposite to the firstsemiconductor layer, wherein the fourth semiconductor layer includes animpurity of an amount that is large enough so as not to be completelydepleted even when a reverse bias voltage is applied between the secondand third semiconductor layers.

In the SOI semiconductor device, the fourth semiconductor layer is notcompletely depleted when a reverse bias voltage is applied between thesecond and third semiconductor layers. As a result, the fourthsemiconductor layer, which is not completely depleted, keeps thepotential almost constant at the bottom of the first semiconductor layerand the depletion layer is easy to extend in the first semiconductorlayer. Also, by applying a reverse bias voltage to the pn junctioncomprising the fourth and first semiconductor layers, a depletion layerextends from the pn junction to the first semiconductor layer.Accordingly, when any reverse bias voltage is applied between the secondand third semiconductor layers, the depletion layer can be evenly extendin the first semiconductor layer and the internal electric field isreduced, so that an SOI semiconductor device with a favorable operatingvoltage at the reverse bias state is realized.

Here, it is preferable to set the impurity amount per unit area in thefourth semiconductor layer as larger than 3×10¹²/cm² or larger than 1.5times the impurity amount per unit area in the first semiconductorlayer. By doing so, the fourth semiconductor layer can be prevented frombeing completely depleted. Also, the depletion layer formed at the pnjunction comprising of the first and fourth semiconductor layers by areverse bias extends more widely on the side of the first semiconductorlayer to help the depletion layer in the first semiconductor layerevenly extend.

The above-mentioned object may also be achieved by the SOI semiconductordevice, wherein an isolation trench is formed in an outer region of thefirst semiconductor layer so as to surround the second and thirdsemiconductor layers and be deep enough to reach the first insulatinglayer, and a second insulating layer is formed on an side wall of theisolation trench. As a result, even if other semiconductor elements areformed adjacent to the SOI semiconductor device on the samesemiconductor substrate, the SOI semiconductor device is not affected bythe potential of the other semiconductor elements and operates withstability. Further, the above-mentioned object may also be achieved bythe SOI semiconductor device, wherein a fifth semiconductor layer withthe same conductivity type as the conductivity type of the fourthsemiconductor layer is formed at an interface between the firstsemiconductor layer and the second insulating layer. As a result, pnjunction separation is realized by the first and fifth semiconductorlayers, and the effects of the potential of the adjacent semiconductorelements are further reduced.

In addition, when the isolation trench is filled with an electricallyconductive material, the electrically conductive material is providedwith an electrode. When an voltage of the same potential as the voltageapplied to the insulating layer is applied to the electrode, the SOIsemiconductor device is electrically shielded. As a result, the effectsof the potential of the adjacent semiconductor elements are furtherreduced.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, advantages and features of the invention willbecome apparent from the following description thereof taken inconjunction with the accompanying drawings which illustrate a specificembodiment of the invention. In the Drawings:

FIG. 1 shows the structure of the n-type high voltage MOS transistor ofa conventional SOI semiconductor device with a dielectric isolationstructure;

FIG. 2 shows the structure of the n-type high voltage MOS transistor ofanother conventional SOI semiconductor device with a dielectricisolation structure;

FIG. 3 is a sectional view of the main structure of an n-type highvoltage MOS transistor according to the first embodiment the presentinvention;

FIG. 4A shows the simulation result of the internal potentialdistribution and depletion layer extension when the n-type high voltageMOS transistor according to the first embodiment is set at a reversebias state by applying a voltage of 0V to a source electrode;

FIG. 4B shows the simulation result of the internal potentialdistribution and depletion layer extension when the n-type high voltageMOS transistor according to the first embodiment is set at a reversebias state by applying a voltage of 0V to a drain electrode;

FIG. 5A shows the simulation result of the internal potentialdistribution and depletion layer extension when the conventional n-typehigh voltage MOS transistor shown in FIG. 1 is set at a reverse biasstate by applying a voltage of 0V to a source electrode;

FIG. 5B shows the simulation result of the internal potentialdistribution and depletion layer extension when the conventional n-typehigh voltage MOS transistor shown in FIG. 1 is set at a reverse biasstate by applying a voltage of 0V to a drain electrode;

FIG. 6A shows relationship between the impurity concentration in ann⁻-type semiconductor layer and the source-drain maximum operatingvoltage when the conventional n-type high voltage MOS transistor and then-type high voltage MOS transistor according to the first embodiment areset at a reverse bias state by applying a voltage of 0V to the sourceelectrode;

FIG. 6B shows relationship between the impurity concentration in ann⁻-type semiconductor layer and the source-drain maximum operatingvoltage when the conventional n-type high voltage MOS transistor and then-type high voltage MOS transistor according to the first embodiment areset at a reverse bias state by applying a voltage of 0V to the drainelectrode;

FIG. 7 shows relationship between the impurity concentration in a p-typesemiconductor layer, which has been formed so as to be adjacent to aninsulator film, and the source-drain maximum operating voltage in then-type high voltage MOS transistor according to the first embodiment;

FIG. 8 is a sectional view of the main structure of an n-type highvoltage MOS transistor according to the second embodiment of the presentinvention;

FIG. 9 is a sectional view of the main structure of an n-type highvoltage MOS transistor according to the third embodiment of the presentinvention;

FIG. 10 is a sectional view of the main structure of an n-type highvoltage MOS transistor according to the fourth embodiment of the presentinvention;

FIG. 11 is a sectional view of the main structure of a high voltage pndiode according to the fifth embodiment of the present invention;

FIG. 12 is a sectional view of the main structure of a p-type highvoltage MOS transistor according to the sixth embodiment of the presentinvention;

FIG. 13 is a sectional view of the main structure of a lateral IGBTaccording to the seventh embodiment of the present invention; and

FIG. 14 is a sectional view of the main structure of a lateral thyristoraccording to the eighth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An explanation of preferred embodiments of the SOI semiconductor deviceaccording to the present invention will be given below with reference tofigures.

The First Embodiment

In the first embodiment, an n-type high voltage MOS transistor will bedescribed as an example of the SOI semiconductor device according to thepresent invention.

(Structure of N-type High Voltage MOS Transistor)

FIG. 3 is a sectional view of the main structure of an n-type highvoltage MOS transistor 200 according to the first embodiment of thepresent invention. As shown in FIG. 3, an n⁻-type semiconductor layer 3overlies a semiconductor substrate 1 via a silicon dioxide film 2 toform the n-type high voltage MOS transistor 200. The n⁻-typesemiconductor layer 3 is the first semiconductor layer and the activelayer of the SOI substrate. The semiconductor substrate 1 is thesupporting substrate of the SOI substrate. The silicon dioxide film 2 isthe first insulator film. While only one MOS transistor is shown in FIG.3, a plurality of MOS transistor elements are actually formed so as tobe adjacent to each other on the same semiconductor substrate. In orderto electrically insulate adjacent elements, an isolation trench 4 isformed in the outer region of the n⁻-type semiconductor layer 3.

The isolation trench 4 is formed by etching so as to reach the silicondioxide film 2. On the side walls of the isolation trench 4, silicondioxide films 5 are formed as the second insulator film. The silicondioxide films 5 and the silicon dioxide film 2 isolate the n⁻-typesemiconductor layer 3 as an island dielectrically isolated from otherelements.

In the space between the silicon dioxide films 5, a polysilicon film 6is filled as a conductive material with a high resistance. Even if thesilicon dioxide films on the opposite side walls are at differentpotentials, the potential gradient is solved by a small current throughthe polysilicon film 6 so that no unnecessary electric field arises inthe isolation trench 4.

On the island n⁻-type semiconductor layer 3, gate oxide films 7, gateelectrodes 8, a p-type semiconductor layer 9, a source electrode 13,n⁺-type semiconductor layers 10, drain electrodes 14, and n⁺-typesemiconductor layers 11 are formed in the manner well known in the art.The p-type semiconductor layer 9 is the second semiconductor layer forforming a channel region. The n⁺-type semiconductor layers 10 are formedso as to be connected to the source electrode 13 and surrounded by thep-type semiconductor layer 9. The n⁻-type semiconductor layers 11 areconnected to the drain electrodes 14 and is the third semiconductorlayer.

On the other hand, at the interface between the island n⁻-typesemiconductor layer 3 and the embedded silicon dioxide film 2, a p-typesemiconductor layer 12 is formed as the fourth semiconductor layer. Thep-type semiconductor layer 12 is set to include impurity of more than3×10¹²/cm² so as not to be completely depleted in the reverse biasstate. On this matter, a more detailed explanation will be given later.

(Manufacturing Method)

An overall explanation of the manufacturing method of the n-type highvoltage MOS transistor 200 will be given below.

The p-type semiconductor layer 12 is formed by injecting an amount ofimpurity that is no smaller than a predetermined amount into the surfaceof the n⁻-type semiconductor layer 3 that has been formed on at leastone of the main surfaces of a semiconductor substrate (referred to the“active layer substrate” in this specification) by the ion implantationor the thermal diffusion. Meanwhile, the silicon dioxide film 2 isformed on the surface of the semiconductor substrate 1, which is thesupporting substrate of the SOI substrate, according to the CVD(Chemical Vapor Deposition) method and the like. The semiconductorsubstrate 1 and the active layer substrate are bonded together with heattreatment so that the silicon dioxide film 2 overlies the p-typesemiconductor layer 12. In this manner, the SOI substrate ismanufactured.

Note that the silicon dioxide film 2 can be formed on the surface of thep-type semiconductor layer 12 on the n⁻-type semiconductor layer 3instead of being formed on the surface of the semiconductor substrate 1.Also, the silicon dioxide film 2 can be formed on both of the surfacesof the semiconductor substrate 1 and the p-type semiconductor layer 12.

The surface of the n⁻-type semiconductor layer 3 is polished so as tohave the desired thickness. The isolation trench 4 is, then, formed soas to reach the silicon dioxide film 2 by etching the SOI substrate fromthe side of the n⁻-type semiconductor layer 3. In etching process, aphoto resist mask is used or a patterned silicon dioxide film or siliconnitride film is used as a mask. After the etching process, the silicondioxide films 5 are formed on the side walls of the isolation trench 4and space between the silicon dioxide films 5 is filled with thepolysilicon film 6 so as to dielectrically isolate the n⁻-typesemiconductor layer 3 as an island.

On the dielectrically isolated island n⁻-type semiconductor layer 3,then, the gate oxide films 7 and the gate electrodes 8 are formed, andthe p-type semiconductor layer 9 for a channel region is formed by ionimplantation and heat treatment. Also in the n⁻-type semiconductor layer3, the n⁺-type semiconductor layers 10, which are to be the source, areformed so as to be surrounded by the p-type semiconductor layer 9 andthe n⁺-type semiconductor layers 11, which are to be the drain, areformed so as not to come in contact with the p-type semiconductor layer9. Finally, the source electrode 13 and the drain electrodes 14 areconnected to the n⁺-type semiconductor layers 10 and the n⁺-typesemiconductor layers 11, respectively to manufacture the n-type highvoltage MOS transistor 200.

Here, the p-type semiconductor layer 12 is formed on the surface of then⁻-type semiconductor layer 3 on at least one of the main surfacesbefore the n⁻-type semiconductor layer 3 and the semiconductor substrate1 are bonded together. Instead, the p-type semiconductor layer 12 can beformed in this way. An active layer substrate with the n⁻-typesemiconductor layer 3 and the semiconductor substrate 1 are bondedtogether so as to sandwich the silicon dioxide film 2. Then, the surfaceof the n⁻-type semiconductor layer 3 is polished so as to have thedesired thickness. After that, the p-type semiconductor layer 12 isformed at the bottom of the n⁻-type semiconductor layer 3 by implantingion from the surface of the n⁻-type semiconductor layer 3 according tothe high energy ion implantation.

Also, while the semiconductor substrate 1 and the active layer substrateare bonded together so as to sandwich the silicon dioxide film 2 in thismanufacturing method, the silicon dioxide film 2 can be formed at thebottom of the n⁻-type semiconductor layer 3 by implanting oxygen ioninto the active layer substrate.

Moreover, while the surface of the n⁻-type semiconductor layer 3 ispolished so as to have the desired thickness in this manufacturingmethod, the thickness can be adjusted in other ways. For instance,hydrogen and the like is implanted into the n⁻-type semiconductor layer3 in advance and the surface of the n⁻-type semiconductor layer 3 ispolished after appropriate degree of heat treatment or pressure.

Here, an explanation of the operating voltage of the n-type high voltageMOS transistor 200 according to the present embodiment will be given.

Generally speaking, a voltage of 0V is applied to the semiconductorsubstrate 1, which is the supporting substrate of the SOI substrate, inthe n-type high voltage MOS transistor 200. Via the gate electrodes 8and the source electrode 13, almost the same degree of voltage, i.e., avoltage “A”, is applied to the p-type semiconductor layer 9 and then⁺-type semiconductor layers 10 so as to set the n-type high voltage MOStransistor 200 at the OFF state. In this condition, a voltage “B”, whichhas a positive potential larger than the voltage “A”, is applied to then⁺-type semiconductor layers 11 via the drain electrodes 14. As aresult, the pn junction diode consisting of the p-type semiconductorlayer 9 and the n⁻-type semiconductor layer 3 is set at the reverse biasstate, and a depletion layer extends from the pn junction interfacebetween the p-type semiconductor layer 9 and the n⁻-type semiconductorlayer 3 into the n⁻-type semiconductor layer 3. Explained later, thedegree of the extension of the depletion layer significantly affects theoperating voltage of the n-type high voltage MOS transistor 200.

While a variety of combination of the voltages “A” and “B” sets then-type high voltage MOS transistor 200 at the reverse bias, the presentembodiment will focus on the operating voltage in the following twoconditions. (1) A voltage of 0V is applied to the semiconductorsubstrate 1, a voltage of 0V is also applied to the source electrode 13as the voltage “A”, and a voltage of 400V is applied to the drainelectrodes 14 as a positive and large voltage, i.e., the voltage “B”(referred to the “first reverse bias state” in this specification). (2)A voltage of −0V is applied to the semiconductor substrate 1, a voltageof 400V −400V is applied to the source electrode 3 as the voltage “A”,and a voltage of 0V is applied to the drain electrodes 14 as the voltage“B” (referred to the “second reverse bias state” in this specification).

FIG. 4A is a diagram showing the simulation result of the internalpotential distribution and the depletion layer extension when the n-typehigh voltage MOS transistor 200 is set at the first reverse bias state.FIG. 4B is a diagram showing the simulation result of the internalpotential distribution and the depletion layer extension when the n-typehigh voltage MOS transistor 200 is set at the second reverse bias state.Each of FIGS. 4A and 4B shows a perspective cross section of theright-half of the n-type high voltage MOS transistor 200.

In each of FIGS. 4A and 4B, the depletion layer extends from the pnjunction interface between the p-type semiconductor layer 9 and then⁻-type semiconductor layer 3 to the depletion layer end that isindicated by the dashed line, i.e., the inside of the n⁻-typesemiconductor layer 3 is completely depleted. As a result, the potentialdistribution inside of the n⁻-type semiconductor layer 3 is so uniformthat the internal electric field is reduced to hardly cause avalanchebreakdown. Generally speaking, the operating voltage of the n-type highvoltage MOS transistor depends on the avalanche breakdown in the n⁻-typesemiconductor layer 3. Accordingly, in the n-type high voltage MOStransistor 200, a favorable operating voltage at the reverse bias statecan be obtained.

On the other hand, in the conventional n-type high voltage MOStransistor 100, a favorable operating voltage at the reverse bias statecan not be always obtained.

FIG. 5A is a diagram showing the simulation result of the internalpotential distribution and the depletion layer extension when the n-typehigh voltage MOS transistor 100 is set at the first reverse bias state.FIG. 5B is a diagram showing the simulation result of the internalpotential distribution and the depletion layer extension when the n-typehigh voltage MOS transistor 100 is set at the second reverse bias state.Each of FIGS. 5A and 5B shows a perspective cross section of the righthalf, i.e., the substantial part of the n-type high voltage MOStransistor 100 shown in FIG. 1.

As shown in FIG. 5A, even in the conventional n-type high voltage MOStransistor 100, the inside of the n⁻-type semiconductor layer 3 iscompletely depleted, the potential distribution in the n⁻-typesemiconductor layer 3 is significantly sparse, and the internal electricfield is reduced in the first reverse bias state, in which the sourcepotential is 0V, as in the case of the present embodiment. As a result,the avalanche breakdown hardly occurs in the n⁻-type semiconductor layer3 and a favorable operating voltage at the reverse bias state can beobtained.

On the other hand, in the second reverse bias state, in which the drainpotential is 0V, a voltage of 0V is applied to both of the n⁺-typesemiconductor layers 11 and the semiconductor substrate 1. As a result,as shown in FIG. 5B, the depletion layer extending from the pn junctioninterface between the p-type semiconductor layer 9 and the n⁻-typesemiconductor layer 3 does not extend enough to reach a region of then⁻-type semiconductor layer 3 under the n⁺-type semiconductor layers 11,i.e., the depletion layer is prevented from extending. As a result, theinternal electric field is not reduced, so that the operating voltage atthe reverse bias state of the n-type high voltage MOS transistordrastically deteriorates. Accordingly, a voltage of −400V can not beapplied as the voltage “A”.

As has been described, in the second reverse bias state, a voltage of 0Vis applied to both the n⁺-type semiconductor layers 11 and thesemiconductor substrate 1, i.e., the n⁺-type semiconductor layers 11 andthe semiconductor substrate 1 are at the same potential. As a result, itis inevitable in the reverse bias state in the conventional n-type highvoltage MOS transistor 100 that the depletion layer area is decreasedand the operating voltage deteriorates.

On the other hand, according to the n-type high voltage MOS transistor200, the depletion layer extends throughout the inside of the n⁻-typesemiconductor layer 3 as shown in FIG. 4B, so that the same level ofreverse bias operating voltage as the case in FIG. 4A is obtained.

More specifically, in addition to having the p-type semiconductor layer12 between the silicon dioxide film 2 and the n-type semiconductor layer3, the impurity concentration in the p-type semiconductor layer 12 isset so as to prevent the p-type semiconductor layer 12 from beingcompletely depleted (higher than 3×10¹²/cm²) according to the presentembodiment. As a result, the p-type semiconductor layer 12 that is notcompletely depleted keeps the potential at the bottom of the n⁻-typesemiconductor layer 3 approximately constant. Also, as a result of thereverse bias applied to the pn junction consisting of the p-typesemiconductor layer 12 and the n⁻-type semiconductor layer 3, thedepletion layer extends from the pn junction to the inside of then⁻-type semiconductor layer 3.

As mentioned above, the operating voltage of the n-type high voltage MOStransistor significantly depends on the avalanche breakdown in then⁻-type semiconductor layer 3. According to the present embodiment,however, the impurity concentration of the p-type semiconductor layer 12is set so as not to completely deplete the p-type semiconductor layer 12even in the second reverse bias state, so that the depletion layerextends throughout the inside of the n⁻-type semiconductor layer 3. As aresult, the potential distribution is uniform and the avalanchebreakdown hardly occurs. Accordingly, a favorable operating voltage atthe reverse bias state can be obtained for the n-type high voltage MOStransistor.

(Relationship Between Impurity Amount in Each Semiconductor Layer andMaximum Operating Voltage)

FIGS. 6A and 6B show relationship between the source-drain maximumoperating voltage and the impurity amount (impurity concentration) inthe n⁻-type semiconductor layer that is to be the active layer of thetransistor in the n-type high voltage MOS transistor 200 (the presentMOS transistor) and the conventional n-type high voltage MOS transistor100 (the conventional MOS transistor). While FIG. 6A shows therelationship between the source-drain maximum operating voltage and theimpurity concentration in the first reverse bias state (the sourcepotential=0V), FIG. 6B shows the relationship in the second reverse biasstate (the drain potential=0V).

In the first reverse bias state, the present MOS transistor and theconventional MOS transistor have almost the same properties as shown inFIG. 6A. Both of the MOS transistors show higher maximum operatingvoltages when the impurity amount in the n⁻-type semiconductor layer 3is 5.0×10¹⁴ to 1.0×10¹⁵/cm³.

On the other hand, in the second reverse bias state, while a favorableoperating voltage at the reverse bias state is obtained for the presentMOS transistor similarly to the case in FIG. 6A, the source-drainmaximum operating voltage drastically deteriorates for the conventionaltransistor as shown in FIG. 6B. Especially, when the impurityconcentration is no higher than 1.0×10¹⁵/cm³, the source-drain maximumoperating voltage of the conventional MOS transistor deteriorates to theextent of approximately half of that of the present MOS transistor.

Accordingly, a favorable source-drain maximum operating voltage can beobtained in both of the first and second reverse bias states for then-type high voltage MOS transistor 200. Especially, when the impurityconcentration in the n⁻-type semiconductor layer 3 is 5.0×10¹⁴ to1.0×10¹⁵/cm³, profound effects can be obtained.

In the present embodiment, as has been described, the operating voltageis improved since the p-type semiconductor layer 12 is not completelydepleted. Note that the size of the depletion layer depends on theimpurity amount in the p-type semiconductor layer 12. Accordingly, it isnecessary not only to interpose the p-type semiconductor layer 12between the n⁻-type semiconductor layer 3 and the silicon dioxide film 2but also to set the impurity amount in the p-type semiconductor layer 12at an appropriate value so as not to completely deplete the p-typesemiconductor layer 12 even if a predetermined reverse bias voltage isapplied.

FIG. 7 is a plot showing the result of an experiment on the dependenceof the source-drain maximum operating voltage on the impurityconcentration in the p-type semiconductor layer 12 in the n-type highvoltage MOS transistor according to the present embodiment. Note thatthe impurity concentration in the n⁻-type semiconductor layer 3 is setat 1.0×10¹⁵/cm³ and the n⁻-type semiconductor layer 3 thickness is setat 20 μm in this experiment.

As shown in FIG. 7, when the impurity concentration in the p-typesemiconductor layer 12 is lower than 3.0×10¹²/cm², the source-drainmaximum operating voltage drastically deteriorates. This can beexplained as follows. When the impurity concentration in the p-typesemiconductor layer 12 becomes lower than 3.0×10¹²/cm², the p-typesemiconductor layer 12 begins to be completely depleted especially inthe second reverse bias state. As a result, the p-type semiconductorlayer 12 stops keeping the potential at the bottom of the n⁻-typesemiconductor layer 3 approximately constant, so that the depletionlayer does not extend evenly. Accordingly, the internal electric fieldlocally concentrates to drastically deteriorate the reverse viasoperating voltage of the n-type high voltage MOS transistor.

On the other hand, when the impurity concentration is no lower than3.0×10¹²/cm², an excellently high operating voltage is obtained. Here,while the maximum operating voltage reaches the critical point when theimpurity concentration becomes 3.0×10¹²/cm², it is favorable to set theimpurity concentration at a value higher than 3.0×10¹²/cm² so as toobtain a stable high operating voltage since the critical point cansensitively change according to environmental temperature.

Meanwhile, when a reverse bias voltage is applied to a pn junctionsemiconductor, a depletion layer is formed so as to sandwich the pnjunction interface. Suppose that the thickness of the entire depletionlayer is “W”, the depletion layer thickness for the p-type semiconductorlayer is “Wp”, and the depletion layer thickness for n-typesemiconductor layer is “Wn”, W=Wp+Wn. It is well known that, supposethat the amounts of impurity per unit area in the p-type semiconductorlayer and the n-type semiconductor layer are “dp” and “dn”,respectively, the thickness “WP” and “Wn” are inversely proportional tothe impurity amount “dp” and “dn” approximately.

Accordingly, as the impurity concentration of the p-type semiconductorlayer 12 increases, the depletion layer is formed more narrowly in thep-type semiconductor layer 12. In the present invention, the maximumimpurity concentration of the p-type semiconductor layer 12 is the upperlimit of the solution of the impurity in the silicon.

More specifically, the upper limit of the solution of boron (B), whichis generally used as the impurity of the P-type semiconductor, is5.0×10²⁰/cm³, which is approximately 1.0×10¹⁷/cm² on a per unit areabasis for a device in practical use. Note that FIG. 7 shows experimentaldata when the impurity concentration of the n⁻-type semiconductor layer3 is 1.0×10¹⁵/cm³ as mentioned earlier. As shown in FIGS. 6A and 6B, itis preferable to set the impurity concentration of the n⁻-typesemiconductor layer 3 as no higher than 1.0×10¹⁵/cm³ to obtain afavorable operating voltage. In addition, consider the fact that thedepletion layer is more narrowly formed in the p-type semiconductorlayer 12 as the impurity concentration of the p-type semiconductor layer12 increases. Under the circumstances, a favorable operating voltage canbe obtained for all the n-type high voltage MOS transistor when thefollowing condition is satisfied. The impurity concentration of thep-type semiconductor layer 12 needs to be higher than the lower limit ofthe impurity concentration of the p-type semiconductor layer 12(3.0×10¹²/cm²) that is required to obtain a favorable operating voltagewhen the impurity concentration of the n⁻-type semiconductor layer 3 isset at the upper limit (1.0×10¹⁵/cm³).

Generally, the impurity amount in the n⁻-type semiconductor layer 3 isset no larger than 1.0×10¹⁵/cm³ for the semiconductor element.Accordingly, when the impurity concentration of the p-type semiconductorlayer 12 is higher than 3.0×10¹²/cm², a favorable operating voltage canbe obtained for all the n-type high voltage MOS transistor.

On the other hand, the impurity concentration of the n⁻-typesemiconductor layer 3, i.e., 1.0×10¹⁵/cm³ is(1.0×10¹⁵)×(2.0×10⁻³)=2.0×10¹²(/cm²) on a per unit area basis since thethickness of the n⁻-type semiconductor layer 3 is set at 20 μm(2.0×10⁻³cm) in this example.

Here, only the condition that the impurity concentration of the p-typesemiconductor layer 12 is higher than the lower limit, i.e.,(3.0×10¹²/cm²), needs to be satisfied. As a result, when the impurityconcentration per unit area of the p-type semiconductor layer 12 is setas higher than (3.0×10¹²/(2.0×10¹²)=1.5 times the impurity concentrationper unit area of the n⁻-type semiconductor layer 3, a favorableoperating voltage can be obtained for all the n-type high voltage MOStransistor.

As has been described, the ratio between the thicknesses of thedepletion layer in the p-type and n-type semiconductors is inverselyproportional to the impurity amounts per unit area of the p-type andn-type semiconductor when a reverse bias voltage is applied to the pnjunction semiconductor. Meanwhile, the impurity concentration per unitarea can be set irrelevant to the thickness of the semiconductor layer.As a result, even if the thickness of the n⁻-type semiconductor layer 3is not 20 μm as in the case of this example, when the impurity amountper unit area in the p-type semiconductor layer 12 is larger than 1.5times the impurity concentration per unit area of the n⁻-typesemiconductor layer 3, a favorable operating voltage can be obtained.

As has been described, in the n-type high voltage MOS transistor 200according to the present embodiment, the p-type semiconductor layer 12,which has a different conductivity type from the n⁻-type semiconductorlayer 3 and the impurity concentration is set to satisfy the conditionthat has been described, is sandwiched between the n⁻-type semiconductorlayer 3 and the silicon dioxide film 2. As a result, the depletion layerin the n⁻-type semiconductor layer 3 is encouraged to evenly extend, sothat the internal electric field is reduced and a favorable reverse biasoperating voltage can be obtained.

While explanations of the structure of the n-type high voltage MOStransistor 200 according to the present embodiment and the impurityamount have been given taking specific examples that is in the first andsecond reverse bias states, the theory that the p-type semiconductorlayer 12 encourage the depletion layer to extend can be similarlyapplied to other reverse bias states. Also, the depletion layer tends tobe prevented from extending most in the second reverse bias state, i.e.,in the condition in which a voltage of 0V is applied to thesemiconductor substrate 1 and the drain electrodes 14 and a negativehigh voltage is applied to the source electrode 13. As a result, whenthe structure and the conditions of the p-type semiconductor layer 12that have been described are realized in all the other reverse biasstates, a favorable operating voltage can be obtained.

The Second Embodiment

FIG. 8 is a sectional view of the main structure of an n-type highvoltage MOS transistor 210 according to the second embodiment of thepresent invention.

The n-type high voltage MOS transistor 210 is different from the n-typehigh voltage MOS transistor 200 in FIG. 3 in forming a p-typesemiconductor layer 15, which has the same conductivity type as thep-type semiconductor layer 12, as the fifth semiconductor layer alongthe interface between the n⁻-type semiconductor layer 3 and the silicondioxide film 5 that has been formed on the side wall of the isolationtrench 4.

In order to encourage to extend the depletion layer throughout theinside of the n⁻-type semiconductor layer 3 even in the reverse biasstate, it is preferable to set the impurity amount per unit area in thep-type semiconductor layer 15 as larger than 3.0×10/cm² as in the caseof the p-type semiconductor layer 12.

The p-type semiconductor layer 15 is formed as follows, for instance.Before the forming of the isolation trench 4 in the n⁻-typesemiconductor layer 3, a p-type semiconductor layer in an area beslightly wider than the isolation trench 4 is formed according to theion implantation so as to reach the silicon dioxide film 2. Then, theisolation trench 4 is formed inside of the p-type semiconductor layer byetching.

With this structure, the n-type high voltage MOS transistor 210 has arelatively improved operating voltage as in the case of the n-type highvoltage MOS transistor 200 in the first embodiment. Also, due to the pnjunction isolation by the p-type semiconductor layer 15 and the n⁻-typesemiconductor layer 3, the effects of the potentials of the adjacentsemiconductor elements can be further prevented.

The Third Embodiment

FIG. 9 is a sectional view of the main structure of an n-type highvoltage MOS transistor 220 according to the third embodiment of thepresent invention. The n-type high voltage MOS transistor 220 isdifferent from the n-type high voltage MOS transistor 210 in beingprovided with n⁺-type semiconductor layers 16 and electrodes 17. Then⁺-type semiconductor layers 16 are formed by implanting impurity intothe surface of the polysilicon film 6 that has been filled in theisolation trench 4. On the n⁺-type semiconductor layers 16, theelectrodes 17 are formed.

With this structure, the n-type high voltage MOS transistor 220 hasalmost the same operating voltage as the n-type high voltage MOStransistors 200 and 210. Also, for instance, when a voltage at the samepotential as the voltage that has been applied to the semiconductorsubstrate 1, i.e., a voltage of a ground potential is applied to then⁺-type semiconductor layers 16 via the electrodes 17, the n-type highvoltage MOS transistor 220 is electrically shielded by the polysiliconfilm 6. As a result, the effects of the potentials of the adjacentsemiconductor elements can be further prevented.

Note that the n⁺-type semiconductor layers 16 formed on the polysiliconfilm 6 are conductive layers for ohmically connecting the electrodes 17.In this respect, p⁺-type semiconductor layers can be formed instead ofthe n⁺-type semiconductor layers 16.

The Fourth Embodiment

FIG. 10 is a sectional view of the main structure of an n-type highvoltage MOS transistor 230 according to the fourth embodiment of thepresent invention. The n-type high voltage MOS transistor 230 isdifferent from the n-type high voltage MOS transistor 200 in FIG. 3 inthe places of the source electrodes 13 and the drain electrode 14. Morespecifically, the source electrodes 13 in the n-type high voltage MOStransistor 230 are formed in places corresponding to the place of thedrain electrodes 14 in the n-type high voltage MOS transistor 200, andthe drain electrode 14 in the n-type high voltage MOS transistor 230 isformed in a place corresponding to the place of the source electrode 13in the n-type high voltage MOS transistor 200. For the n-type highvoltage MOS transistor 230, the p-type semiconductor layers 9 forchannel regions, the source electrodes 13, and the n⁺-type semiconductorlayers 10, which are formed so as to be connected to the sourceelectrodes 13 and be surrounded by the p-type semiconductor layers 9,are formed on outer regions of the surface of the island n⁻-typesemiconductor layer 3. On the other hand, the drain electrode 14 and then⁺-type semiconductor layer 11 that is connected to the drain electrode14 as the third semiconductor layer are formed at the center of thesurface of the island n⁻-type semiconductor layer 3. With thisstructure, an n-type high voltage MOS transistor with an improvedreverse bias operating voltage can be realized as in the case of then-type high voltage MOS transistor 200 in the first embodiment.

The Fifth Embodiment

FIG. 11 is a sectional view of the main structure of a high voltage pndiode 240 according to the fifth embodiment of the present invention.Unlike the n-type high voltage MOS transistor 200, the gate oxide film7, the gate electrode 8, and the n⁺-type semiconductor layers 10 thatare formed so as to be connected to the gate electrodes 8 and to besurrounded by the p-type semiconductor layer 9 in FIG. 3 are not formedfor the high voltage pn diode 240. For the high voltage pn diode 240, ap⁺-type semiconductor layer 18 is formed so as to be surrounded by thep-type semiconductor layer 9 instead of the n⁺-type semiconductor layers10, an anode electrode 19 instead of the source electrode 13, andcathode electrodes 20 instead of the drain electrodes 14.

In the high voltage pn diode 240, the p-type semiconductor layer 9, then⁺-type semiconductor layers 11, the n⁻-type semiconductor layer 3, andthe p-type semiconductor layer 12 have the same structures as in then-type high voltage MOS transistor 200 according to the firstembodiment. As a result, the high voltage pn diode 240 has an improvedreverse bias operating voltage.

The Sixth Embodiment

FIG. 12 is a sectional view of the main structure of a p-type highvoltage MOS transistor 250 according to the sixth embodiment of thepresent invention. The island n⁻-type semiconductor layer 3 in thep-type high voltage MOS transistor 250 is formed in the same manner asin the n-type high voltage MOS transistor 200. On the n⁻-typesemiconductor layer 3, the gate oxide films 7, the gate electrodes 8, ann-type semiconductor layer 22, the source electrode 13, p⁺-typesemiconductor layers 23, the drain electrodes 14, p⁺-type semiconductorlayers 24, and the p⁻-type semiconductor layers 21 are formed. Then-type semiconductor layer 22 is formed as the third semiconductor layerfor forming a channel region. The p⁺-type semiconductor layers 23 areformed so as to be connected to the source electrode 13 and to besurrounded by p⁻-type semiconductor layers 22. The p⁺-type semiconductorlayers 24 are formed as the second semiconductor layer connected to thedrain electrodes 14. The p⁻-type semiconductor layers 21 are formed soas to surround the p⁺-type semiconductor layers 24 and so that a part ofeach of the p⁻-type semiconductor layers 21 contacts the n-typesemiconductor layer 22. At the interface between the island n⁻-typesemiconductor layer 3 and the silicon dioxide film 2, the p-typesemiconductor layer 12 is formed as the fourth semiconductor layer.

In the p-type high voltage MOS transistor 250, the p⁻-type semiconductorlayers 21 and the p⁺-type semiconductor layers 24, the n-typesemiconductor layer 22, and the p⁺-type semiconductor layers 23 areformed instead of the n⁺-type semiconductor layers 11, the p-typesemiconductor layer 9, and the n⁺-type semiconductor layers 10 in then-type high voltage MOS transistor 200 according to the firstembodiment, respectively to have different conductivity types from then-type high voltage MOS transistor 200. Apart from the conductivitytypes of the semiconductor layers, the p-type high voltage MOStransistor 250 has almost the same structure as the n-type high voltageMOS transistor 200. Also, the p-type high voltage MOS transistor 250 hasan improved reverse bias operating voltage.

The Seventh Embodiment

FIG. 13 is a sectional view of the main structure of a lateral insulatedgate bipolar transistor (IGBT) 260 according to the seventh embodimentof the present invention. The island n⁻-type semiconductor layer 3 inthe lateral IGBT 260 is formed in the same manner as in the n-type highvoltage MOS transistor 200. On the n⁻-type semiconductor layer 3, thegate oxide films 7, the gate electrode 8, the p-type semiconductor layer9, the source electrode 13, the n⁺-type semiconductor layers 10, thedrain electrodes 14, and n-type semiconductor layers 26 are formed. Thep-type semiconductor layer 9 is formed as the second semiconductor layerfor forming a channel region. The n⁺-type semiconductor layers 10 areformed so as to be connected to the source electrode 13 and to besurrounded by the p-type semiconductor layer 9. The n-type semiconductorlayers 26 are formed so as to surround p⁺-type semiconductor layers 25that are connected to the drain electrodes 14. At the interface betweenthe island n⁻-type semiconductor layer 3 and the silicon dioxide film 2,the p-type semiconductor layer 12 is formed as the fourth semiconductorlayer. The basic structure of the pn diode consisting of the p-typesemiconductor layer 9, the n-type semiconductor layers 26, and then⁻-type semiconductor layer 3 in the lateral IGBT 260 is the same as inthe n-type high voltage MOS transistor 200 according to the firstembodiment. Also, the same effects as the first embodiment can beobtained by the p-type semiconductor layer 12 at the bottom of theisland n⁻-type semiconductor layer 3. As a result, the lateral IGBT 260also has an improved reverse bias operating voltage.

The Eighth Embodiment

FIG. 14 is a sectional view of the main structure of a lateral thyristor270 according to the eighth embodiment of the present invention. Theisland n⁻-type semiconductor layer 3 in the lateral thyristor 270 isformed in the same manner as in the n-type high voltage MOS transistor200. On the n⁻-type semiconductor layer 3, p-type semiconductor layers27 and 28, an anode electrode 19, a p⁺-type semiconductor layer 30, acathode electrode 20, an n⁺-type semiconductor layer 29, a P-typecontrol gate electrode 33, a p⁺-type semiconductor layer 31, N-typecontrol gate electrodes 34, and n⁺-type semiconductor layers 32 areformed. The p-type semiconductor layers 27 and 28 are formed as thesecond semiconductor layer. The p⁺-type semiconductor layer 30 is formedso as to be connected to the anode electrode 19 and to be surrounded bythe p-type semiconductor layer 28. The n⁻-type semiconductor layer 29 isformed so as to be connected to the cathode electrode 20 and to besurrounded by the p-type semiconductor layer 27. The p⁺-typesemiconductor layer 31 is formed so as to be connected to the P-typecontrol gate electrode 33 and to be surrounded by the p-typesemiconductor layer 27. The n⁺-type semiconductor layers 32 are formedso as to be connected to the N-type control gate electrodes 34 as thethird semiconductor layer.

At the interface between the island n⁻-type semiconductor layer 3 andthe silicon dioxide film 2, the p-type semiconductor layer 12 is formedas the fourth semiconductor layer. The lateral thyristor 270 has a pnpnstructure consisting of the p-type semiconductor layer 28, the n⁻-typesemiconductor layer 3, the p-type semiconductor layer 27, and then⁺-type semiconductor layer 29. The basic operations by the pnpnstructure is the same as the pn diode in the n-type high voltage MOStransistor 200. Also, the same effects as the first embodiment can beobtained by the p-type semiconductor layer 12 at the bottom of theisland n⁻-type semiconductor layer 3. As a result, the lateral thyristor270 also has an improved reverse bias operating voltage.

(Other Possible Modifications)

The present invention is not limited to the preferred embodiments thathave been described. Other possible modifications are given below.

(1) In the explanation of the preferred embodiments, the n⁻-typesemiconductor layer is used as the first semiconductor layer that is theactive layer of the SOI substrate. The same effects can be obtained ifthe p⁻-type semiconductor layer is used as the first semiconductorlayer. In this case, however, the n-type semiconductor layer needs to beformed as the fourth semiconductor layer at the interface between thep⁻-type semiconductor layer and the silicon dioxide film that has beenembedded at the bottom of the first semiconductor layer.

(2) In the preferred embodiments, the semiconductor substrate 1 is usedas the supporting substrate of the SOI substrate. The same effects canbe obtained if an insulating substrate is used instead of thesemiconductor substrate 1. In this case, however, it is preferable toset the potential on the underside of the SOI semiconductor device evenby forming a metal film with a constant thickness on the back of theinsulating substrate according to the evaporation, for instance. (3) Inthe preferred embodiments, the silicon dioxide film is used as theinsulating film formed at the bottom of the n⁻-type semiconductor layer3 and the side walls of the isolation trench 4. The same effects can beobtained if another insulating film, for instance, the silicon nitridefilm is used instead of the silicon dioxide film.

Although the present invention has been fully described by way ofexamples with reference to the accompanying drawings, it is to be notedthat various changes and modifications will be apparent to those skilledin the art. Therefore, unless such changes and modifications depart fromthe scope of the present invention, they should by construed as beingincluded therein.

1. An SOI semiconductor device comprising: a first semiconductor layer;a second semiconductor layer that is formed on a first part of a firstmain surface of the first semiconductor layer; a third semiconductorlayer with a conductivity type different from a conductivity type of thesecond semiconductor layer, the third semiconductor layer being formedon a second part of the first main surface of the first semiconductorlayer, the second part being separated from the first part; a fourthsemiconductor layer with a conductivity type different from aconductivity type of the first semiconductor layer, the fourthsemiconductor layer being formed on a second main surface of the firstsemiconductor layer; and a first insulating layer that is formed on amain surface of the fourth semiconductor layer opposite to the firstsemiconductor layer, wherein the fourth semiconductor layer includes animpurity of an amount greater than 3×10¹²/cm² which is not completelydepleted even when a reverse bias voltage is applied between the secondand third semiconductor layers, the reverse bias voltage making apotential of a drain lower than a potential of a source a potential of asource lower than a potential of a drain.
 2. The SOI semiconductordevice according to claim 1, wherein the amount of the impurity per unitarea in the fourth semiconductor layer is larger than 1.5 times anamount of an impurity per unit area in the first semiconductor layer. 3.The SOI semiconductor device according to claim 1, wherein the firstsemiconductor layer includes 5×10¹⁴/cm³ to 1×10¹⁵/cm³ of an impurity. 4.The SOI semiconductor device according to claim 1, wherein an isolationtrench is formed in an outer region of the first semiconductor layer soas to surround the second and third semiconductor layers and be deepenough to reach the first insulating layer, and a second insulatinglayer is formed on an side wall of the isolation trench.
 5. The SOIsemiconductor device according to claim 4, wherein a fifth semiconductorlayer with the same conductivity type as the conductivity type of thefourth semiconductor layer is formed at an interface between the firstsemiconductor layer and the second insulating layer.
 6. The SOIsemiconductor device according to claim 5, wherein the fifthsemiconductor layer includes more than 3×10¹²/cm² of an impurity.
 7. TheSOI semiconductor device according to claim 5, wherein an amount of theimpurity per unit area in the fifth semiconductor layer is larger than1.5 times an amount of an impurity per unit area in the firstsemiconductor layer.
 8. The SOI semiconductor device according to claim4, wherein an interior space of the isolation trench is filled with anelectrically conductive material.
 9. The SOI semiconductor deviceaccording to claim 8, wherein the electrically conductive material isprovided with an electrode.
 10. The SOI semiconductor device accordingto claim 9, wherein the electrically conductive material is polysilicon,and the electrode is ohmically connected to the polysilicon via aconductive semiconductor layer.
 11. The SOI semiconductor deviceaccording to claim 1, wherein a semiconductor substrate is joined to thefourth semiconductor layer at the main surface of the fourthsemiconductor layer opposite to the first semiconductor layer, and thefirst insulating layer is an oxide film that has been formed on at leastone of (1) the main surface of the fourth semiconductor layer oppositeto the first semiconductor layer and (2) a surface of the semiconductorsubstrate at which the semiconductor substrate is joined to the fourthsemiconductor layer.
 12. The SOI semiconductor device according to claim1, wherein the first insulating layer is an insulating substrate, and ametal film is formed on a main surface of the insulating substrateopposite to the fourth semiconductor layer.
 13. The SOI semiconductordevice according to claim 1, wherein the SOI semiconductor device is aMOS transistor.
 14. The SOI semiconductor device according to claim 1,wherein the SOI semiconductor device is a pn diode.
 15. The SOIsemiconductor device according to claim 1, wherein the SOI semiconductordevice is a lateral insulated gate bipolar transistor.
 16. The SOIsemiconductor device according to claim 1, wherein the SOI semiconductordevice is a lateral thyristor.
 17. An SOI semiconductor devicecomprising: a first semiconductor layer; a second semiconductor layerthat is formed on a first part of a first main surface of the firstsemiconductor layer; a third semiconductor layer with a conductivitytype different from a conductivity type of the second semiconductorlayer, the third semiconductor layer being formed on a second part ofthe first main surface of the first semiconductor layer, the second partbeing separated from the first part; a fourth semiconductor layer with aconductivity type different from a conductivity type of the firstsemiconductor layer, the fourth semiconductor layer being formed on asecond main surface of the first semiconductor layer; a first insulatinglayer that is formed on a main surface of the fourth semiconductor layeropposite to the first semiconductor layer; a source electrode, and adrain electrode wherein the fourth semiconductor layer includes animpurity of an amount that is large enough so as not to be completelydepleted even when a reverse bias voltage is applied between the secondand the third semiconductor layers, and the drain electrode is set at apotential lower higher than a potential of a source, the impurity amountis greater than 3×10¹²/cm² and equal to or less than 1.0×10¹⁷/cm². 18.The SOI semiconductor device according to claim 17 wherein the firstsemiconductor layer includes 5×10¹⁴/cm³ to 1×10¹⁵/cm³ of an impurity.19. The SOI semiconductor device according to claim 18 wherein theamount of the impurity per unit area in the fourth semiconductor layeris larger than 1.5 times an amount of an impurity per unit area in thefirst semiconductor layer.
 20. In a system for improving the operatingvoltage of a semiconductor device having means for applying voltages tothe semiconductor device, the improvement of an SOI semiconductor devicecomprising: a first semiconductor layer; a second semiconductor layerthat is formed on a first part of a first main surface of the firstsemiconductor layer; a third semiconductor layer with a conductivitytype different from a conductivity type of the second semiconductorlayer, the third semiconductor layer being formed on a second part ofthe first main surface of the first semiconductor layer, the second partbeing separated from the first part; a fourth semiconductor layer with aconductivity type different from a conductivity type of the firstsemiconductor layer, the fourth semiconductor layer being formed on asecond main surface of the first semiconductor layer; and a firstinsulating layer that is formed on a main surface of the fourthsemiconductor layer opposite to the first semiconductor layer, whereinthe fourth semiconductor layer includes an impurity of an amount greaterthan 3×10¹²/cm² which is not completely depleted even when areverse-bias voltage is applied between the second and thirdsemiconductor layers, the reverse bias voltage making a potential of adrain lower than a potential of a source a potential of a source lowerthan a potential of a drain.